The present invention relates to a method of forming fine patterns of a semiconductor device and, more particularly, to a method of forming fine patterns of a semiconductor device, including a spacer patterning process.
Recently, with the increase in the degree of integration of semiconductor devices, the entire chip area is increased in proportion to an increase in the capacity of memory, but the area of a cell region in which the dense patterns of the memory cells are actually formed is reduced. To secure a desired capacity of a memory device, a greater number of patterns have to be formed within a limited cell region. Accordingly, the critical dimension of a pattern gradually decreases and becomes finer. To form a pattern having a fine critical dimension as described above, there is a need for the development of a lithography process.
The lithography process is used to form a photoresist pattern, defining fine patterns, by coating a photoresist over a substrate, performing an exposure process on the photoresist using an exposure mask having the fine patterns defined therein using a light source having a wavelength such as 365 nm, 248 nm, 193 nm, and 153 nm, and then performing a development process.
The resolution R of such a lithography process is determined by the equation R=k1×λ/NA where ‘λ’ is the wavelength of a light source, ‘NA’ is a numerical aperture, and ‘k1’ indicates a process constant. It is difficult to reduce the value of the process constant in a typical manner because the process constant has a physical limit. Accordingly, new photoresist materials having a high reactivity to the short wavelength light source have to be developed along with an exposure apparatus using the short wavelength. This makes it difficult to form a fine pattern reaching the critical dimension equal to the short wavelength or less.
For the above reason, there was developed a Double Patterning Technology (hereinafter referred to as a ‘DPT’) for forming fine patterns by performing the exposure process twice (dual exposure) using the same exposure mask without a change of the exposure apparatus or exposure conditions. Furthermore, a Spacer Patterning Technology (hereinafter referred to as a ‘SPT’), which is similar to the DPT, but does not need dual exposure or dual patterning, was developed and is being researched.
FIG. 1 is a schematic diagram showing a conventional DPT. A positive DPT is shown on the left side of FIG. 1, and a negative DPT is shown on the right side of FIG. 1.
Referring first to the left side of FIG. 1, an amorphous carbon layer 120, a second hard mask layer 130, and a first hard mask layer 140 are sequentially formed over a semiconductor substrate 110. First photoresist patterns 152 of a line and space type are formed on the first hard mask layer 140. In the first photoresist patterns 152, the critical dimension ratio of a line and a space preferably is 1:3.
Next, the first hard mask layer 140 is etched using the first photoresist patterns 152 as a mask, thereby forming first hard mask patterns 142 of a line and space type. Second photoresist patterns 156 of a line and space type are formed between the first hard mask patterns 142 using a photolithography process. The second hard mask layer 130 is etched using the first hard mask patterns 142 and the second photoresist patterns 156 as a mask, thereby forming second hard mask patterns 132.
Here, the second hard mask patterns 132 are formed in a line and space pattern in which the critical dimension ratio of the line and space is 1:1. Accordingly, the second hard mask patterns 132, each having a half critical dimension as compared with the first photoresist pattern 152, can be obtained under the same exposure apparatus and conditions.
The negative DPT shown on the right side of FIG. 1 can also have the same effects as the positive DPT. The negative DPT is identical with the positive DPT except that the critical dimension of a line and a space in first photoresist patterns 154 and second photoresist patterns 158 is 3:1, and a detailed description thereof is omitted.
FIG. 2 is a schematic diagram showing a conventional spacer patterning process. A positive spacer patterning process is shown on the left side of FIG. 2, and a negative spacer patterning process is shown on the right side of FIG. 2.
Referring first to the left side of FIG. 2, an amorphous carbon layer 220, a second hard mask layer 230, and a first hard mask layer 240 are sequentially formed over a semiconductor substrate 220. First photoresist patterns 252 of a line and space type are formed on the first hard mask layer 240. The critical dimension ratio of the line and the space in the first photoresist patterns 252 preferably is 1:3.
Next, the first hard mask layer 240 is etched using the first photoresist patterns 252 as a mask, thereby forming first hard mask patterns 242 of a line and space type. A spacer 262 having the same width as the first hard mask pattern 242 is formed on the sidewalls of each of the first hard mask patterns 242. The first hard mask patterns 242 are then removed. The second hard mask layer 230 is etched using the remaining spacers 262 as a mask, thereby forming second hard mask patterns 232.
Here, the second hard mask patterns 232 are formed in a line and space pattern in which the critical dimension ratio of the line and the space is 1:1. Accordingly, the second hard mask patterns 232, each having a half critical dimension as compared with the first photoresist pattern 252, can be obtained under the same exposure apparatus and conditions.
The negative spacer patterning process shown on the right side of FIG. 2 can also have the same effects as the positive spacer patterning process. The negative spacer patterning process differs from the positive spacer patterning process in that, after forming spacers 264, a dielectric interlayer 270 is deposited, the spacers 264 are removed, and the second hard mask layer 230 is etched using the first hard mask patterns 244 and the dielectric interlayer 270 as a mask. That is, in the positive spacer patterning process, the final patterns having the same shape as the spacers are formed, whereas in the negative spacer patterning process, the final patterns having the same shape as the spaces with no spacer are formed.
Such a spacer patterning process is advantageous in that it can reduce the cost of production because an additional masking process is not required compared with the DPT and thus it can drastically reduce a misalignment problem occurring at the second masking step in the DPT. Accordingly, more active research is being carried on the spacer patterning process than on the DPT. However, even in a method of forming the fine patterns of a semiconductor device using the spacer patterning process, research are still carried out in order to further reduce the number of process steps.